1. Field of the Invention
The present invention relates to a method of forming flash memory. More particularly, the present invention relates to a self-aligned process for forming the source lines of an ETOX flash memory.
2. Description of the Related Art
ETOX flash memory is a type of conventional erasable programmable read only memory (EPROM) that also includes a thin tunnel oxide layer in its structure. In fact, the name ETOX refers to an EPROM with a tunnel oxide layer.
FIG. 1 is a schematic top view of a portion of an ETOX flash memory structure. FIG. 2A is a cross-sectional view along line A-A' of FIG. 1 showing a unit memory cell of the ETOX flash memory, while FIG. 2B is a cross-sectional view along line B-B' of FIG. 1.
As shown in FIGS. 1, 2A and 2B, an ETOX flash memory structure is formed in several steps. First, longitudinal device isolation structures 110 are formed in a substrate 100. In general, with a critical dimension larger than 0.25 .mu.m, field oxide (FOX) is frequently used to form the device isolation structures 110. However, for devices having a critical dimension smaller than 0.25 .mu.m, shallow trench isolation (STI) structures are used more often. In the subsequent step, a tunnel oxide layer 120, a floating gate 130, an oxide/nitride/oxide (ONO) composite dielectric layer 140 and a control gate 150 are sequentially formed over the substrate 100. The floating gate 130, the ONO dielectric layer 140 and the control gate 150 together constitute a stacked gate.
The device isolation structures 110 in the region for forming the desired source lines are removed and so trenches 190 are formed in the substrate 100. Using the stacked gate as a mask, an ion implantation is carried out to implant ions into the exposed substrate 100. Hence, a source line 160 and a drain terminal 170 are formed in the substrate 100 on each side of the gate stack.
Subsequent operation includes forming a bit line contact 180 above the drain terminal 170 for connecting the drain terminal 170 to the bit line (not shown) over the stacked gate. The bit lines run in a direction parallel to the device isolation structures 110 but perpendicular to the stacked gates. The source line 160 runs in a direction perpendicular to the device isolation structures 110 but parallel to the stacked gates. Since subsequent operations necessary for forming a complete ETOX flash memory should be familiar to persons skilled in the art of semiconductor manufacturing, detailed descriptions of the steps are omitted here.
In the aforementioned process of removing the device isolation structures 110 in preparation for implanting ions into the substrate 100 to form the source line, a number of problems are often encountered. FIG. 3 is a cross-sectional view along line III-III' of the source line 160 in FIG. 1. In FIG. 3, cross-sectional structures of adjacent memory cells are also drawn. After the removal of device isolation structures 110, trenches 190 are formed in the substrate 100. The subsequent implantation of ions into the exposed substrate 100 results in the formation of source lines 160. Since STI structures 110 are often used when critical dimension of device drops to below 0.25 .mu.m, trenches 190 with high aspect ratio are formed after the device isolation structures 110 are removed. Hence, no matter at what angle the incoming ion beam is set, whether it comes from direction 200a, 200b or 200c, only a portion of the substrate surface of each trench 190 such as 195a, 195b or 195c, is doped. Unless the ion beam changes its angle of tilt and adjusts its implantation energy level continuously, doped ions cannot form a continuous conductive band that links regions like 195a, 195b and 195c in each trench 190. Because continuous adjustment of the ion beam to form a uniformly doped substrate layer is a difficult process, most often than not, electrical resistivity of the source lines 160 rises and discontinuity problems intensify.
As resistivity of the source line 160 rises, operational speed of the ETOX flash memory drops. On the other hand, if the level of concentration of dopants in the substrate 100 is raised to increase the electrical conductivity of the source lines 160, the band-to-band tunneling current may increase, resulting in a larger leakage current. Furthermore, a source line contact (not shown in the figure) must be erected for every 32 bits if the electrical resistivity of the source lines is too high. Hence, the ultimate level of integration for the ETOX flash memory is restricted.